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| author |   Ben Skeggs <bskeggs@redhat.com> | 2020-06-21 11:25:06 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2020-07-24 18:51:01 +1000 |
| commit | c4c751885efb951a65f3a4df123fe08464dddbba (patch) | |
| tree | 9cd469bccf11df16c15827c50b494ac75075b3b9 /drivers/gpu/drm/nouveau/dispnv50/headc37d.c | |
| parent | drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_view() (diff) | |
| download | wireguard-linux-c4c751885efb951a65f3a4df123fe08464dddbba.tar.xz wireguard-linux-c4c751885efb951a65f3a4df123fe08464dddbba.zip | |
drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_mode()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/dispnv50/headc37d.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 40 |
1 files changed, 30 insertions, 10 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 7553f1198509..e397ababa3e7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -187,20 +187,40 @@ headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) const int i = head->base.index; int ret; - if ((ret = PUSH_WAIT(push, 13))) + if ((ret = PUSH_WAIT(push, 15))) return ret; - PUSH_NVSQ(push, NVC37D, 0x2064 + (i * 0x400), m->v.active << 16 | m->h.active, - 0x2068 + (i * 0x400), m->v.synce << 16 | m->h.synce, - 0x206c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, - 0x2070 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, - 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); - PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace, - 0x200c + (i * 0x400), m->clock * 1000); - PUSH_NVSQ(push, NVC37D, 0x2028 + (i * 0x400), m->clock * 1000); + PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i), + NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | + NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), + + HEAD_SET_RASTER_SYNC_END(i), + NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | + NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), + + HEAD_SET_RASTER_BLANK_END(i), + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), + + HEAD_SET_RASTER_BLANK_START(i), + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); + + //XXX: + PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace); + + PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), + NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), + NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ - PUSH_NVSQ(push, NVC37D, 0x2030 + (i * 0x400), 0x00000124); + PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i), + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) | + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) | + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE)); return 0; } |