diff options
| author |   Marek Vasut <marex@denx.de> | 2022-07-10 21:44:35 +0200 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2022-07-19 10:39:00 +0200 |
| commit | de2b4917843cd433d0f1c279123f75801dcd0c1e (patch) | |
| tree | 3007dc5af1ccadbd74733dc17867919595af0ab3 /drivers/gpu/drm/panel | |
| parent | drm/panel/panel-sitronix-st7701: Adjust porch control bitfield name (diff) | |
| download | wireguard-linux-de2b4917843cd433d0f1c279123f75801dcd0c1e.tar.xz wireguard-linux-de2b4917843cd433d0f1c279123f75801dcd0c1e.zip | |
drm/panel/panel-sitronix-st7701: Infer horizontal pixel count from TFT mode
The horizontal pixel count is a property of the TFT matrix. Currently the
driver hard-codes content of this register to specific value which is
only compatible with one TFT matrix, likely the TS8550B one.
Calculate the horizontal pixel count from the mode instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-7-marex@denx.de
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sitronix-st7701.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index ce33b362dc13..ae545eba5cb0 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -74,11 +74,9 @@ #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) -#define DSI_INVSEL_DEFAULT GENMASK(5, 4) -#define DSI_INVSEL_NLINV GENMASK(2, 0) -#define DSI_INVSEL_RTNI GENMASK(2, 1) -#define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI -#define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV) +#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) +#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) +#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) /* Command2, BK1 bytes */ #define DSI_CMD2_BK1_VRHA_SET 0x45 @@ -114,6 +112,7 @@ struct st7701_panel_desc { /* TFT matrix driver configuration, panel specific. */ const u8 pv_gamma[16]; /* Positive voltage gamma control */ const u8 nv_gamma[16]; /* Negative voltage gamma control */ + const u8 nlinv; /* Inversion selection */ }; struct st7701 { @@ -186,8 +185,17 @@ static void st7701_init_sequence(struct st7701 *st7701) mode->vtotal - mode->vsync_end), FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, mode->vsync_start - mode->vdisplay)); + /* + * Horizontal pixel count configuration: + * PCLK = 512 + (RTNI[4:0] * 16) + * The PCLK is number of pixel clock per line, which matches + * mode htotal. The minimum is 512 PCLK. + */ ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, - DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1); + DSI_CMD2_BK0_INVSEL_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), + FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, + DIV_ROUND_UP(mode->htotal, 16))); /* Command2, BK1 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, @@ -410,6 +418,7 @@ static const struct st7701_panel_desc ts8550b_desc = { CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, + .nlinv = 7, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi) |