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authorMikko Perttunen <mperttunen@nvidia.com>2017-08-02 12:55:05 +0300
committerThierry Reding <treding@nvidia.com>2017-08-17 17:57:06 +0200
commit4ac45eb8d17c1a998182c302bd023ecb055bd9ee (patch)
treefe8175fd876a5b689efb2aca83e3446daceea077 /drivers/gpu/host1x/hw/syncpt_hw.c
parentgpu: host1x: Don't fail on NULL bo physical address (diff)
downloadwireguard-linux-4ac45eb8d17c1a998182c302bd023ecb055bd9ee.tar.xz
wireguard-linux-4ac45eb8d17c1a998182c302bd023ecb055bd9ee.zip
gpu: host1x: Fix bitshift/mask multipliers
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate register or field offsets. This worked fine on ARMv7, but now that BITS_PER_LONG is 64 but our registers are still 32-bit things are broken. Fix by replacing.. - BIT_WORD with (x / 32) - BIT_MASK with BIT(x % 32) - BITS_PER_LONG with 32 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/host1x/hw/syncpt_hw.c')
-rw-r--r--drivers/gpu/host1x/hw/syncpt_hw.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
index c93f74fcce72..7b0270d60742 100644
--- a/drivers/gpu/host1x/hw/syncpt_hw.c
+++ b/drivers/gpu/host1x/hw/syncpt_hw.c
@@ -89,7 +89,7 @@ static int syncpt_cpu_incr(struct host1x_syncpt *sp)
host1x_syncpt_idle(sp))
return -EINVAL;
- host1x_sync_writel(host, BIT_MASK(sp->id),
+ host1x_sync_writel(host, BIT(sp->id % 32),
HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
wmb();