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| author |   Anton Tikhomirov <av.tikhomirov@samsung.com> | 2012-03-06 14:05:49 +0900 |
|---|---|---|
| committer |   Felipe Balbi <balbi@ti.com> | 2012-04-10 19:11:44 +0300 |
| commit | f7a83fe19336125d7eb26488788dc66c03f2c08e (patch) | |
| tree | acad855cd590802ff2ff8d6122cfadb8a17db7b5 /drivers/i2c/algos/i2c-algo-bit.c | |
| parent | usb: fsl_udc_core: prime status stage once data stage has primed (diff) | |
| download | wireguard-linux-f7a83fe19336125d7eb26488788dc66c03f2c08e.tar.xz wireguard-linux-f7a83fe19336125d7eb26488788dc66c03f2c08e.zip | |
usb: s3c-hsotg: Fix TX FIFOs allocation
According to documentation, TX FIFO_number index starts from 1.
For IN endpoint FIFO 0 we use GNPTXFSIZ register for programming
the size and memory start address.
Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/i2c/algos/i2c-algo-bit.c')
0 files changed, 0 insertions, 0 deletions