diff options
| author |   Tomi Valkeinen <tomi.valkeinen@ti.com> | 2020-03-25 13:15:09 +0100 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-04-14 12:51:47 +0200 |
| commit | 355357457a5880ddeb776e0f61bbb74f49dc5f4c (patch) | |
| tree | cdef3c0e2913583f706fa7828c4355b2c1819d17 /drivers/media/platform | |
| parent | media: ti-vpe: cal: improve wait for CIO resetdone (diff) | |
| download | wireguard-linux-355357457a5880ddeb776e0f61bbb74f49dc5f4c.tar.xz wireguard-linux-355357457a5880ddeb776e0f61bbb74f49dc5f4c.zip | |
media: ti-vpe: cal: improve wait for stop-state
Sometimes there is a timeout when waiting for the Stop-State. Testing
shows that sometimes we need to wait more than what the current code
does. It is not clear how long this wait can be, but it is based on how
quickly the sensor provides a valid clock, and how quickly CAL syncs to
it.
Change the code to make it more obvious how long we'll wait, and set a
wider range for usleep_range. Increase the timeout to 750ms.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/platform')
| -rw-r--r-- | drivers/media/platform/ti-vpe/cal.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 38f1ae63f26a..3ee1053cb2de 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -845,14 +845,15 @@ static void csi2_wait_complexio_reset(struct cal_ctx *ctx) static void csi2_wait_stop_state(struct cal_ctx *ctx) { - int i; + unsigned long timeout; - for (i = 0; i < 10; i++) { + timeout = jiffies + msecs_to_jiffies(750); + while (time_before(jiffies, timeout)) { if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0) break; - usleep_range(1000, 1100); + usleep_range(500, 5000); } if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), |