diff options
| author |   Piotr Sroka <piotrs@cadence.com> | 2020-02-10 10:55:27 +0100 |
|---|---|---|
| committer |   Miquel Raynal <miquel.raynal@bootlin.com> | 2020-03-11 16:17:55 +0100 |
| commit | 9bf1903bed7a2e84f5a8deedb38f7e0ac5e8bfc6 (patch) | |
| tree | 4674c3f69323089b1e414d77fc13c2323bd3f0a8 /drivers/mtd | |
| parent | mtd: rawnand: cadence: fix the calculation of the avaialble OOB size (diff) | |
| download | wireguard-linux-9bf1903bed7a2e84f5a8deedb38f7e0ac5e8bfc6.tar.xz wireguard-linux-9bf1903bed7a2e84f5a8deedb38f7e0ac5e8bfc6.zip | |
mtd: rawnand: cadence: change bad block marker size
Increase bad block marker size from one byte to two bytes.
Bad block marker is handled by skip bytes feature of HPNFC.
Controller expects this value to be an even number.
Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subsystem")
Cc: stable@vger.kernel.org
Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1581328530-29966-3-git-send-email-piotrs@cadence.com
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/raw/cadence-nand-controller.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c index 2ebfd0934739..5c1bbb05ab51 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -2612,12 +2612,9 @@ int cadence_nand_attach_chip(struct nand_chip *chip) chip->options |= NAND_NO_SUBPAGE_WRITE; cdns_chip->bbm_offs = chip->badblockpos; - if (chip->options & NAND_BUSWIDTH_16) { - cdns_chip->bbm_offs &= ~0x01; - cdns_chip->bbm_len = 2; - } else { - cdns_chip->bbm_len = 1; - } + cdns_chip->bbm_offs &= ~0x01; + /* this value should be even number */ + cdns_chip->bbm_len = 2; ret = nand_ecc_choose_conf(chip, &cdns_ctrl->ecc_caps, |