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| author |   Jianbo Liu <jianbol@nvidia.com> | 2021-11-01 02:40:28 +0000 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2022-07-02 11:58:28 -0700 |
| commit | 17c5da03879b97da91968e3db58c19e1679e457c (patch) | |
| tree | 58bff7277d642b02aadd3869d11dd1e51566f9cd /drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h | |
| parent | net/mlx5e: Get or put meter by the index of tc police action (diff) | |
| download | wireguard-linux-17c5da03879b97da91968e3db58c19e1679e457c.tar.xz wireguard-linux-17c5da03879b97da91968e3db58c19e1679e457c.zip | |
net/mlx5e: Add generic macros to use metadata register mapping
There are many definitions to get bits and mask for different types of
metadata register mapping, add generic macros to unify them.
Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Reviewed-by: Ariel Levkovich <lariel@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h index 00a3ba862afb..6a9933925c4f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h @@ -84,10 +84,8 @@ struct mlx5_ct_attr { .mlen = ESW_ZONE_ID_BITS,\ } -#define REG_MAPPING_MLEN(reg) (mlx5e_tc_attr_to_reg_mappings[reg].mlen) -#define REG_MAPPING_MOFFSET(reg) (mlx5e_tc_attr_to_reg_mappings[reg].moffset) -#define MLX5_CT_ZONE_BITS (mlx5e_tc_attr_to_reg_mappings[ZONE_TO_REG].mlen) -#define MLX5_CT_ZONE_MASK GENMASK(MLX5_CT_ZONE_BITS - 1, 0) +#define MLX5_CT_ZONE_BITS MLX5_REG_MAPPING_MBITS(ZONE_TO_REG) +#define MLX5_CT_ZONE_MASK MLX5_REG_MAPPING_MASK(ZONE_TO_REG) #if IS_ENABLED(CONFIG_MLX5_TC_CT) |