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| author |   Julia Lawall <Julia.Lawall@inria.fr> | 2020-04-30 21:51:32 +0200 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-04-30 17:48:26 -0700 |
| commit | 865308373ed49c9fb05720d14cbf1315349b32a9 (patch) | |
| tree | a68b66d18f101e2d55524d5cdb0d3abcf6c2ade0 /drivers/net/ethernet/pensando/ionic/ionic_lif.c | |
| parent | net: bridge: vlan: Add a schedule point during VLAN processing (diff) | |
| download | wireguard-linux-865308373ed49c9fb05720d14cbf1315349b32a9.tar.xz wireguard-linux-865308373ed49c9fb05720d14cbf1315349b32a9.zip | |
dp83640: reverse arguments to list_add_tail
In this code, it appears that phyter_clocks is a list head, based on
the previous list_for_each, and that clock->list is intended to be a
list element, given that it has just been initialized in
dp83640_clock_init. Accordingly, switch the arguments to
list_add_tail, which takes the list head as the second argument.
Fixes: cb646e2b02b27 ("ptp: Added a clock driver for the National Semiconductor PHYTER.")
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions