diff options
| author |   Tomer Tayar <Tomer.Tayar@cavium.com> | 2017-04-06 15:58:30 +0300 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2017-04-06 14:26:31 -0700 |
| commit | 60afed72f51c7445aa06dc953b05f5672b607860 (patch) | |
| tree | 01739ed7b696f08f2d03d388030516b1e55e22ed /drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | |
| parent | qed: Don't use main-ptt in unrelated flows (diff) | |
| download | wireguard-linux-60afed72f51c7445aa06dc953b05f5672b607860.tar.xz wireguard-linux-60afed72f51c7445aa06dc953b05f5672b607860.zip | |
qed: Configure cacheline size in HW
Default HW configuration is optimal for an architecture where cache
line size is 64B.
During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_reg_addr.h')
| -rw-r--r-- | drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h index 6d4ac7e2ee83..e65397360ab4 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h +++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h @@ -1551,6 +1551,7 @@ #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL +#define PSWRQ2_REG_WR_MBS0 0x240400UL #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL |