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| author |   Vincent Cheng <vincent.cheng.xh@renesas.com> | 2020-05-01 23:35:38 -0400 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-05-02 16:31:45 -0700 |
| commit | 425d2b1c563826cf73e204172919fb40b7c45f1d (patch) | |
| tree | 88a887ab348617f37fab2e90fe5ba76eddccebe6 /drivers/net/phy/phy.c | |
| parent | ptp: Add adjust_phase to ptp_clock_caps capability. (diff) | |
| download | wireguard-linux-425d2b1c563826cf73e204172919fb40b7c45f1d.tar.xz wireguard-linux-425d2b1c563826cf73e204172919fb40b7c45f1d.zip | |
ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.
Add idtcm_adjphase() to support PHC write phase mode.
Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/phy.c')
0 files changed, 0 insertions, 0 deletions