path: root/drivers/pci/controller/cadence/pcie-cadence-host.c
diff options
authorKishon Vijay Abraham I <kishon@ti.com>2020-07-22 16:33:15 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2020-08-03 14:49:55 +0100
commitf3e25911a430ed16ec209929183df762fe9c785b (patch)
treea5825786199ff58ac96b494d21c8f869fe1100b1 /drivers/pci/controller/cadence/pcie-cadence-host.c
parentdt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC (diff)
PCI: j721e: Add TI J721E PCIe driver
Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence-host.c')
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 89d26324b2a8..8d86560196aa 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -23,8 +23,8 @@ static u8 bar_aperture_mask[] = {
[RP_BAR1] = 0xF,
-static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
- int where)
+void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
+ int where)
struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);