diff options
author | Kishon Vijay Abraham I <kishon@ti.com> | 2020-07-22 16:33:15 +0530 |
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committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-08-03 14:49:55 +0100 |
commit | f3e25911a430ed16ec209929183df762fe9c785b (patch) | |
tree | a5825786199ff58ac96b494d21c8f869fe1100b1 /drivers/pci/controller/cadence/pcie-cadence.h | |
parent | dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC (diff) | |
download | wireguard-linux-f3e25911a430ed16ec209929183df762fe9c785b.tar.xz wireguard-linux-f3e25911a430ed16ec209929183df762fe9c785b.zip |
PCI: j721e: Add TI J721E PCIe driver
Add support for PCIe controller in J721E SoC. The controller uses the
Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller
will work in both host mode and device mode.
Some of the features of the controller are:
*) Supports both RC mode and EP mode
*) Supports MSI and MSI-X support
*) Supports upto GEN3 speed mode
*) Supports SR-IOV capability
*) Ability to route all transactions via SMMU (support will be added
in a later patch).
Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.h')
-rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index dd910a1c30fb..00e44256c3e8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -475,11 +475,19 @@ static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } + +static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + return NULL; +} #endif #ifdef CONFIG_PCIE_CADENCE_EP |