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| author |   Anshuman Khandual <anshuman.khandual@arm.com> | 2021-06-15 15:02:58 +0530 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2021-06-15 19:03:24 +0100 |
| commit | 9163f01130304fab1f74683d7d44632da7bda637 (patch) | |
| tree | e3d561784e3a287c37e4b75e716d39b97c63417e /drivers/pci/controller/dwc/pci-keystone.c | |
| parent | arm64: mm: Pass original fault address to handle_mm_fault() (diff) | |
| download | wireguard-linux-9163f01130304fab1f74683d7d44632da7bda637.tar.xz wireguard-linux-9163f01130304fab1f74683d7d44632da7bda637.zip | |
arm64/mm: Fix ttbr0 values stored in struct thread_info for software-pan
When using CONFIG_ARM64_SW_TTBR0_PAN, a task's thread_info::ttbr0 must be
the TTBR0_EL1 value used to run userspace. With 52-bit PAs, the PA must be
packed into the TTBR using phys_to_ttbr(), but we forget to do this in some
of the SW PAN code. Thus, if the value is installed into TTBR0_EL1 (as may
happen in the uaccess routines), this could result in UNPREDICTABLE
behaviour.
Since hardware with 52-bit PA support almost certainly has HW PAN, which
will be used in preference, this shouldn't be a practical issue, but let's
fix this for consistency.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Fixes: 529c4b05a3cb ("arm64: handle 52-bit addresses in TTBR")
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/1623749578-11231-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-keystone.c')
0 files changed, 0 insertions, 0 deletions