diff options
| author |   Rob Herring <robh@kernel.org> | 2020-08-20 21:54:15 -0600 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-09-10 16:50:53 +0100 |
| commit | 441e48fdf0b403218805b320d93de5caeafdcb1d (patch) | |
| tree | 76bbe68dec65d50ac790ab216ca13671f59c86f2 /drivers/pci/controller/dwc/pcie-designware.c | |
| parent | PCI: dwc: Centralize link gen setting (diff) | |
| download | wireguard-linux-441e48fdf0b403218805b320d93de5caeafdcb1d.tar.xz wireguard-linux-441e48fdf0b403218805b320d93de5caeafdcb1d.zip | |
PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.
Link: https://lore.kernel.org/r/20200821035420.380495-36-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 62a6735ada9e..5240153c15ba 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -551,6 +551,7 @@ void dw_pcie_setup(struct dw_pcie *pci) val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); of_property_read_u32(np, "num-lanes", &pci->num_lanes); |