Merge branch 'pci/controller/qcom'

- Select PCI Power Control Slot driver so slot voltage rails can be turned
  on/off if described in Root Port device tree node (Qiang Yu)

- Parse only PCI bridge child nodes in device tree, skipping unrelated
  nodes such as OPP (Operating Performance Points), which caused probe
  failures (Krishna Chaitanya Chundru)

- Add 8.0 GT/s and 32.0 GT/s equalization settings (Ziyue Zhang)

- Fix typo in CURSOR macro names (Ziyue Zhang)

- Consolidate Root Port 'phy' and 'reset' properties in struct
  qcom_pcie_port, regardless of whether we got them from the Root Port node
  or the host bridge node (Manivannan Sadhasivam)

- Fetch and map the ELBI register space in the DWC core rather than in each
  driver individually (Krishna Chaitanya Chundru)

- Enable ECAM mechanism in DWC core by setting up iATU with 'CFG Shift
  Feature' and use this in the qcom driver (Krishna Chaitanya Chundru)

* pci/controller/qcom:
  PCI: dwc: Support ECAM mechanism by enabling iATU 'CFG Shift Feature'
  PCI: qcom: Prepare for the DWC ECAM enablement
  PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'
  PCI: dwc: Add support for ELBI resource mapping
  PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
  PCI: qcom: Fix macro typo for CURSOR
  PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
  PCI: qcom: Restrict port parsing only to PCIe bridge child nodes
  PCI: qcom: Select PCI Power Control Slot driver

1 files changed, 9 insertions, 1 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 1d7c2b27005f..c644216995f6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -167,6 +167,14 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
 		}
 	}
 
+	/* ELBI is an optional resource */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
+	if (res) {
+		pci->elbi_base = devm_ioremap_resource(pci->dev, res);
+		if (IS_ERR(pci->elbi_base))
+			return PTR_ERR(pci->elbi_base);
+	}
+
 	/* LLDD is supposed to manually switch the clocks and resets state */
 	if (dw_pcie_cap_is(pci, REQ_RES)) {
 		ret = dw_pcie_get_clocks(pci);
@@ -500,7 +508,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
-	val = PCIE_ATU_ENABLE;
+	val = PCIE_ATU_ENABLE | atu->ctrl2;
 	if (atu->type == PCIE_ATU_TYPE_MSG) {
 		/* The data-less messages only for now */
 		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;