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| author |   Vidya Sagar <vidyas@nvidia.com> | 2019-08-13 17:06:27 +0530 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-09-08 13:00:53 +0100 |
| commit | 56e15a238d92788a2d09e0c5c26a5de1b3156931 (patch) | |
| tree | c852b822e71559d402df4ec97027d5601e5b1a81 /drivers/pci/controller/dwc/pcie-designware.c | |
| parent | phy: tegra: Add PCIe PIPE2UPHY support (diff) | |
| download | wireguard-linux-56e15a238d92788a2d09e0c5c26a5de1b3156931.tar.xz wireguard-linux-56e15a238d92788a2d09e0c5c26a5de1b3156931.zip | |
PCI: tegra: Add Tegra194 PCIe support
Add support for Synopsys DesignWare core IP based PCIe host controller
present in the Tegra194 SoC.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 59eaeeb21dbe..4d6690b6ca36 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -456,7 +456,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); } - dev_err(pci->dev, "Phy link never came up\n"); + dev_info(pci->dev, "Phy link never came up\n"); return -ETIMEDOUT; } |