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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-07-03 14:08:45 +0200 |
|---|---|---|
| committer |   Manivannan Sadhasivam <mani@kernel.org> | 2025-08-19 20:05:51 +0530 |
| commit | a895dc47ceba63feb711905440585cf2b16e9ce2 (patch) | |
| tree | f953fc7a73b9429d429dd89f2c744f68d0299394 /drivers/pci/controller/dwc/pcie-qcom-common.c | |
| parent | Linux 6.17-rc1 (diff) | |
| download | wireguard-linux-a895dc47ceba63feb711905440585cf2b16e9ce2.tar.xz wireguard-linux-a895dc47ceba63feb711905440585cf2b16e9ce2.zip | |
PCI: mediatek-gen3: Implement sys clock ready time setting
In preparation to add support for the PCI-Express Gen3 controller
found in newer MediaTek SoCs, such as the Dimensity 9400 MT6991
and the MT8196 Chromebook SoC, add the definition for the PCIE
Resource Control register and a new sys_clk_rdy_time_us variable
in platform data.
If sys_clk_rdy_time_us is found (> 0), set the new value in the
aforementioned register only after configuring the controller to
RC mode, as this may otherwise be reset.
Overriding the register defaults for SYS_CLK_RDY_TIME allows to
work around sys_clk_rdy signal glitching in MT6991 and MT8196.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[mani: used FIELD_MODIFY() to simplify mask and update]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250703120847.121826-2-angelogioacchino.delregno@collabora.com
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.c')
0 files changed, 0 insertions, 0 deletions