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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:19 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:19 -0500 |
| commit | dde4b05e26c5077d751ba1ca71aaf2d0bfa8a180 (patch) | |
| tree | d570fe2d63b7b51256fee0675824d6130486a29d /drivers/pci/controller/dwc/pcie-qcom-common.c | |
| parent | Merge branch 'pci/controller/keystone' (diff) | |
| parent | PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC (diff) | |
| download | wireguard-linux-dde4b05e26c5077d751ba1ca71aaf2d0bfa8a180.tar.xz wireguard-linux-dde4b05e26c5077d751ba1ca71aaf2d0bfa8a180.zip | |
Merge branch 'pci/controller/mediatek-gen3'
- Add optional sys clock ready time setting to avoid sys_clk_rdy signal
glitching in MT6991 and MT8196 (AngeloGioacchino Del Regno)
- Add DT binding and driver support for MT6991 and MT8196 (AngeloGioacchino
Del Regno)
* pci/controller/mediatek-gen3:
PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC
dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
PCI: mediatek-gen3: Implement sys clock ready time setting
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.c')
0 files changed, 0 insertions, 0 deletions