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| author |   Conor Dooley <conor.dooley@microchip.com> | 2023-01-29 23:57:01 +0000 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-02-14 16:00:02 -0800 |
| commit | 2a5303b499b18de7179ee1b4ab759880fb02ec9c (patch) | |
| tree | a533026a7b541542e8c2223fa5a31aff278b94c1 /drivers/pci/controller/dwc | |
| parent | Merge patch series "riscv: improve boot time isa extensions handling" (diff) | |
| download | wireguard-linux-2a5303b499b18de7179ee1b4ab759880fb02ec9c.tar.xz wireguard-linux-2a5303b499b18de7179ee1b4ab759880fb02ec9c.zip | |
Documentation: riscv: fix insufficient list item indent
When adding the ISA string ordering rules, I didn't sufficiently indent
one of the list items.
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/linux-doc/202301300743.bp7Dpazv-lkp@intel.com/
Fixes: f07b2b3f9d47 ("Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com>
Link: https://lore.kernel.org/r/20230129235701.2393241-1-conor@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
0 files changed, 0 insertions, 0 deletions