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author | 2020-12-18 09:15:12 +0200 | |
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committer | 2020-12-18 09:15:12 +0200 | |
commit | 500050f0d28868af302a3c24d7d1d0191521286e (patch) | |
tree | 7c4366836fcf5c7d7be4292f60d76876b3c463a0 /drivers/pci/controller/dwc | |
parent | ARM: omap2: pmic-cpcap: fix maximum voltage to be consistent with defaults on xt875 (diff) | |
parent | ARM: OMAP1: OSK: fix ohci-omap breakage (diff) | |
download | wireguard-linux-500050f0d28868af302a3c24d7d1d0191521286e.tar.xz wireguard-linux-500050f0d28868af302a3c24d7d1d0191521286e.zip |
Merge branch 'fixes-omap3' into fixes
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-host.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 674f32db85ca..44c2a6572199 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { - struct resource_entry *entry = - resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + struct resource_entry *tmp, *entry = NULL; + + /* Get last memory resource entry */ + resource_list_for_each_entry(tmp, &pp->bridge->windows) + if (resource_type(tmp->res) == IORESOURCE_MEM) + entry = tmp; dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, entry->res->start, |