diff options
| author |   Mark Brown <broonie@kernel.org> | 2023-04-11 16:11:32 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-04-11 16:11:32 +0100 |
| commit | 53e59b5c4645236f0014d3cc5c24bc71ad3f6120 (patch) | |
| tree | 64c6005d6ffd496454fffb05b584ffb7011e12b4 /drivers/pci/controller/dwc | |
| parent | regulator: qcom_smd: Add MP5496 S1 regulator (diff) | |
| parent | regulator: fan53555: Add support for RK860X (diff) | |
| download | wireguard-linux-53e59b5c4645236f0014d3cc5c24bc71ad3f6120.tar.xz wireguard-linux-53e59b5c4645236f0014d3cc5c24bc71ad3f6120.zip | |
Add support for Rockchip RK860X regulators
Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>:
This patch series introduces support for the Rockchip RK860X regulators,
while also providing a few fixes and improvements to the existing fan53555
driver.
RK8600/RK8601 are quite similar to the FAN53555 regulators.
RK8602/RK8603 are a bit different, having a wider output voltage
selection range, from 0.5 V to 1.5 V in 6.25 mV steps. They are used
in the Rock 5B board to power the ARM Cortex-A76 cores and the NPU.
Diffstat (limited to 'drivers/pci/controller/dwc')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 53a16b8b6ac2..8e33e6e59e68 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1001,11 +1001,6 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); } - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - val &= ~PORT_LINK_FAST_LINK_MODE; - val |= PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - if (dw_pcie_cap_is(pci, CDM_CHECK)) { val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | @@ -1013,6 +1008,11 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + if (!pci->num_lanes) { dev_dbg(pci->dev, "Using h/w default number of lanes\n"); return; |