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authorZachary Zhang <zhangzg@marvell.com>2018-06-29 11:16:19 +0200
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-07-06 13:08:04 +0100
commit91a2968e245d6ba616db37001fa1a043078b1a65 (patch)
tree906ddc6ff9ca5422173063e8ee1dbbee0a615964 /drivers/pci/controller/pci-aardvark.c
parentPCI: aardvark: Remove PCIe outbound window configuration (diff)
downloadwireguard-linux-91a2968e245d6ba616db37001fa1a043078b1a65.tar.xz
wireguard-linux-91a2968e245d6ba616db37001fa1a043078b1a65.zip
PCI: aardvark: Size bridges before resources allocation
The PCIE I/O and MEM resource allocation mechanism is that root bus goes through the following steps: 1. Check PCI bridges' range and computes I/O and Mem base/limits. 2. Sort all subordinate devices I/O and MEM resource requirements and allocate the resources and writes/updates subordinate devices' requirements to PCI bridges I/O and Mem MEM/limits registers. Currently, PCI Aardvark driver only handles the second step and lacks the first step, so there is an I/O and MEM resource allocation failure when using a PCI switch. This commit fixes that by sizing bridges before doing the resource allocation. Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Zachary Zhang <zhangzg@marvell.com> [Thomas: edit commit log.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: <stable@vger.kernel.org>
Diffstat (limited to 'drivers/pci/controller/pci-aardvark.c')
-rw-r--r--drivers/pci/controller/pci-aardvark.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index c9c72595bd20..10543ed7b500 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -906,6 +906,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
bus = bridge->bus;
+ pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
list_for_each_entry(child, &bus->children, node)