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| author |   Manikanta Maddireddy <mmaddireddy@nvidia.com> | 2019-06-18 23:31:48 +0530 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-06-20 17:20:40 +0100 |
| commit | 7763cc24e2103a54eb43bbe46fca59ddab77c2f2 (patch) | |
| tree | 2478b926ff3727e111791e17f88363a9dab17ad1 /drivers/pci/controller/pci-tegra.c | |
| parent | PCI: tegra: Program UPHY electrical settings for Tegra210 (diff) | |
| download | wireguard-linux-7763cc24e2103a54eb43bbe46fca59ddab77c2f2.tar.xz wireguard-linux-7763cc24e2103a54eb43bbe46fca59ddab77c2f2.zip | |
PCI: tegra: Enable opportunistic UpdateFC and ACK
Enable opportunistic UpdateFC and ACK to allow data link layer send
pending ACKs and UpdateFC packets when link is idle instead of waiting
for timers to expire. This improves the PCIe performance due to better
utilization of PCIe bandwidth.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pci/controller/pci-tegra.c')
| -rw-r--r-- | drivers/pci/controller/pci-tegra.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 2d0a23b2c7bb..cd69c43c9a0c 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -204,7 +204,9 @@ #define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff #define RP_VEND_XP 0x00000f00 -#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) +#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_CTL1 0x00000f48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -529,6 +531,12 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_CTL1); value |= RP_VEND_CTL1_ERPT; writel(value, port->base + RP_VEND_CTL1); + + /* Optimal settings to enhance bandwidth */ + value = readl(port->base + RP_VEND_XP); + value |= RP_VEND_XP_OPPORTUNISTIC_ACK; + value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; + writel(value, port->base + RP_VEND_XP); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) |