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| author |   Alan Douglas <adouglas@cadence.com> | 2018-10-11 17:15:54 +0100 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-10-12 12:09:29 +0100 |
| commit | e81e36a96bb56f243b5ac1d114c37c086761595b (patch) | |
| tree | 058ae1c4f9f2d2e7f37f5c27dde6f891edef32b7 /drivers/pci/controller/pcie-cadence-ep.c | |
| parent | PCI: cadence: Use AXI region 0 to signal interrupts from EP (diff) | |
| download | wireguard-linux-e81e36a96bb56f243b5ac1d114c37c086761595b.tar.xz wireguard-linux-e81e36a96bb56f243b5ac1d114c37c086761595b.zip | |
PCI: cadence: Write MSI data with 32bits
According to the PCIe specification, although the MSI data is only
16bits, the upper 16bits should be written as 0. Use writel
instead of writew when writing the MSI data to the host.
Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/pcie-cadence-ep.c')
| -rw-r--r-- | drivers/pci/controller/pcie-cadence-ep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index 6692654798d4..c3a088910f48 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -355,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); ep->irq_pci_fn = fn; } - writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); return 0; } |