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| author |   Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2020-06-16 18:26:54 +0530 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2020-08-05 17:09:15 -0500 |
| commit | 508f610648b97012d39f97590e3f3f1059471607 (patch) | |
| tree | 322dc138439194f7544dd3d172f7c6d29d85277d /drivers/pci/controller/pcie-iproc-platform.c | |
| parent | PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port (diff) | |
| download | wireguard-linux-508f610648b97012d39f97590e3f3f1059471607.tar.xz wireguard-linux-508f610648b97012d39f97590e3f3f1059471607.zip | |
PCI: xilinx-cpm: Add Versal CPM Root Port driver
Add support for Versal CPM as Root Port.
The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
block for CPM along with the integrated bridge can function as PCIe Root
Port.
Bridge error and legacy interrupts in Versal CPM are handled using Versal
CPM specific interrupt line.
[bhelgaas: fold in kerneldoc fix from
https://lore.kernel.org/linux-acpi/20200729201224.26799-7-krzk@kernel.org/]
Link: https://lore.kernel.org/r/1592312214-9347-3-git-send-email-bharat.kumar.gogada@xilinx.com
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'drivers/pci/controller/pcie-iproc-platform.c')
0 files changed, 0 insertions, 0 deletions