diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-05-07 13:33:18 +0100 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-05-22 12:35:32 +0100 |
| commit | 2a6d0d63d99956a66f6605832f11755d74a41951 (patch) | |
| tree | 1e783e301c1fdd9520dc73592a17c02c2797c47e /drivers/pci/controller/pcie-rcar.h | |
| parent | dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller (diff) | |
| download | wireguard-linux-2a6d0d63d99956a66f6605832f11755d74a41951.tar.xz wireguard-linux-2a6d0d63d99956a66f6605832f11755d74a41951.zip | |
PCI: rcar: Add endpoint mode support
Add support for R-Car PCIe controller to work in endpoint mode.
Link: https://lore.kernel.org/r/1588854799-13710-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Diffstat (limited to 'drivers/pci/controller/pcie-rcar.h')
| -rw-r--r-- | drivers/pci/controller/pcie-rcar.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h index 97640e16af58..d4c698b5f821 100644 --- a/drivers/pci/controller/pcie-rcar.h +++ b/drivers/pci/controller/pcie-rcar.h @@ -17,6 +17,7 @@ #define PCIECDR 0x000020 #define PCIEMSR 0x000028 #define PCIEINTXR 0x000400 +#define ASTINTX BIT(16) #define PCIEPHYSR 0x0007f0 #define PHYRDY BIT(0) #define PCIEMSITXR 0x000840 @@ -55,12 +56,20 @@ /* Configuration */ #define PCICONF(x) (0x010000 + ((x) * 0x4)) +#define INTDIS BIT(10) #define PMCAP(x) (0x010040 + ((x) * 0x4)) +#define MSICAP(x) (0x010050 + ((x) * 0x4)) +#define MSICAP0_MSIE BIT(16) +#define MSICAP0_MMESCAP_OFFSET 17 +#define MSICAP0_MMESE_OFFSET 20 +#define MSICAP0_MMESE_MASK GENMASK(22, 20) #define EXPCAP(x) (0x010070 + ((x) * 0x4)) #define VCCAP(x) (0x010100 + ((x) * 0x4)) /* link layer */ +#define IDSETR0 0x011000 #define IDSETR1 0x011004 +#define SUBIDSETR 0x011024 #define TLCTLR 0x011048 #define MACSR 0x011054 #define SPCHGFIN BIT(4) |