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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2022-10-05 17:32:55 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-10-05 17:32:55 -0500 |
| commit | 84aabff88098af3121498443abe48ad489550f58 (patch) | |
| tree | 64ac05c0822370a6b7347e4f36fe8071dd52c989 /drivers/pci/controller | |
| parent | Merge branch 'remotes/lorenzo/pci/apple' (diff) | |
| parent | PCI: pci-bridge-emul: Set position of PCI capabilities to real HW value (diff) | |
| download | wireguard-linux-84aabff88098af3121498443abe48ad489550f58.tar.xz wireguard-linux-84aabff88098af3121498443abe48ad489550f58.zip | |
Merge branch 'remotes/lorenzo/pci/bridge-emul'
- In an emulated PCI bridge, set Capability offsets so they match the
hardware offsets shown by U-Boot (Pali Rohár)
* remotes/lorenzo/pci/bridge-emul:
PCI: pci-bridge-emul: Set position of PCI capabilities to real HW value
Diffstat (limited to 'drivers/pci/controller')
| -rw-r--r-- | drivers/pci/controller/pci-aardvark.c | 1 | ||||
| -rw-r--r-- | drivers/pci/controller/pci-mvebu.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7cc51cfb8a13..ba36bbc5897d 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1081,6 +1081,7 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; bridge->has_pcie = true; + bridge->pcie_start = PCIE_CORE_PCIEXP_CAP; bridge->data = pcie; bridge->ops = &advk_pci_bridge_emul_ops; diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index af915c951f06..0fdbb5585fec 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -946,6 +946,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) bridge->subsystem_vendor_id = ssdev_id & 0xffff; bridge->subsystem_id = ssdev_id >> 16; bridge->has_pcie = true; + bridge->pcie_start = PCIE_CAP_PCIEXP; bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops; |