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| author |   Rafael J. Wysocki <rjw@sisk.pl> | 2009-01-24 00:23:22 +0100 |
|---|---|---|
| committer |   Jesse Barnes <jbarnes@hobbes.lan> | 2009-03-19 19:29:25 -0700 |
| commit | b43d451385ef833e0696032aac2629da04d46c59 (patch) | |
| tree | 8bc4e838fdef893934d2cee19ae8f2629549bd4f /drivers/pci/pcie/portdrv.h | |
| parent | PCI/MSI: Introduce pci_msix_table_size() (diff) | |
| download | wireguard-linux-b43d451385ef833e0696032aac2629da04d46c59.tar.xz wireguard-linux-b43d451385ef833e0696032aac2629da04d46c59.zip | |
PCI/PCIe portdrv: Fix allocation of interrupts
If MSI-X interrupt mode is used by the PCI Express port driver, too
many vectors are allocated and it is not ensured that the right
vectors will be used for the right services. Namely, the PCI Express
specification states that both PCI Express native PME and PCI Express
hotplug will always use the same MSI or MSI-X message for signalling
interrupts, which implies that the same vector will be used by both
of them. Also, the VC service does not use interrupts at all.
Moreover, is not clear which of the vectors allocated by
pci_enable_msix() in the current code will be used for PME and
hotplug and which of them will be used for AER if all of these
services are configured.
For these reasons, rework the allocation of interrupts for PCI
Express ports so that if MSI-X are enabled, the right vectors will be
used for the right purposes.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/pcie/portdrv.h')
| -rw-r--r-- | drivers/pci/pcie/portdrv.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index ad4d082a0344..5b818bd835ef 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -25,6 +25,12 @@ #define PCIE_CAPABILITIES_REG 0x2 #define PCIE_SLOT_CAPABILITIES_REG 0x14 #define PCIE_PORT_DEVICE_MAXSERVICES 4 +#define PCIE_PORT_MSI_VECTOR_MASK 0x1f +/* + * According to the PCI Express Base Specification 2.0, the indices of the MSI-X + * table entires used by port services must not exceed 31 + */ +#define PCIE_PORT_MAX_MSIX_ENTRIES 32 #define get_descriptor_id(type, service) (((type - 4) << 4) | service) |