diff options
| author |   Yicong Yang <yangyicong@hisilicon.com> | 2020-03-13 17:53:47 +0800 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2020-03-18 17:43:14 -0500 |
| commit | 58a3862a10a317a81097ab0c78aecebabb1704f5 (patch) | |
| tree | b324cdaf0a1b4aeee268fb6d0ab6fc5f431ec5da /drivers/pci/pcie | |
| parent | Linux 5.6-rc1 (diff) | |
| download | wireguard-linux-58a3862a10a317a81097ab0c78aecebabb1704f5.tar.xz wireguard-linux-58a3862a10a317a81097ab0c78aecebabb1704f5.zip | |
PCI/ASPM: Clear the correct bits when enabling L1 substates
In pcie_config_aspm_l1ss(), we cleared the wrong bits when enabling ASPM L1
Substates. Instead of the L1.x enable bits (PCI_L1SS_CTL1_L1SS_MASK, 0xf), we
cleared the Link Activation Interrupt Enable bit (PCI_L1SS_CAP_L1_PM_SS,
0x10).
Clear the L1.x enable bits before writing the new L1.x configuration.
[bhelgaas: changelog]
Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings")
Link: https://lore.kernel.org/r/1584093227-1292-1-git-send-email-yangyicong@hisilicon.com
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.11+
Diffstat (limited to 'drivers/pci/pcie')
| -rw-r--r-- | drivers/pci/pcie/aspm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 0dcd44308228..c2596e79ec63 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) /* Enable what we need to enable */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CAP_L1_PM_SS, val); + PCI_L1SS_CTL1_L1SS_MASK, val); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CAP_L1_PM_SS, val); + PCI_L1SS_CTL1_L1SS_MASK, val); } static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |