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authorBjorn Helgaas <bhelgaas@google.com>2019-03-06 15:30:09 -0600
committerBjorn Helgaas <bhelgaas@google.com>2019-03-06 15:30:09 -0600
commit2fcc19b3410734b1896ba3e9fee1df9036e801fd (patch)
treeb8949091280f63c890a18ec48b8ef1049a200969 /drivers/pci/probe.c
parentMerge branch 'pci/aer' (diff)
parentPCI/ASPM: Save LTR Capability for suspend/resume (diff)
downloadwireguard-linux-2fcc19b3410734b1896ba3e9fee1df9036e801fd.tar.xz
wireguard-linux-2fcc19b3410734b1896ba3e9fee1df9036e801fd.zip
Merge branch 'pci/aspm'
- Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) * pci/aspm: PCI/ASPM: Save LTR Capability for suspend/resume PCI/ASPM: Use LTR if already enabled by platform
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c36
1 files changed, 23 insertions, 13 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 43e6583417ce..1078195f244a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2069,11 +2069,8 @@ static void pci_configure_ltr(struct pci_dev *dev)
{
#ifdef CONFIG_PCIEASPM
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
- u32 cap;
struct pci_dev *bridge;
-
- if (!host->native_ltr)
- return;
+ u32 cap, ctl;
if (!pci_is_pcie(dev))
return;
@@ -2082,22 +2079,35 @@ static void pci_configure_ltr(struct pci_dev *dev)
if (!(cap & PCI_EXP_DEVCAP2_LTR))
return;
- /*
- * Software must not enable LTR in an Endpoint unless the Root
- * Complex and all intermediate Switches indicate support for LTR.
- * PCIe r3.1, sec 6.18.
- */
- if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
- dev->ltr_path = 1;
- else {
+ pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
+ if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
+ dev->ltr_path = 1;
+ return;
+ }
+
bridge = pci_upstream_bridge(dev);
if (bridge && bridge->ltr_path)
dev->ltr_path = 1;
+
+ return;
}
- if (dev->ltr_path)
+ if (!host->native_ltr)
+ return;
+
+ /*
+ * Software must not enable LTR in an Endpoint unless the Root
+ * Complex and all intermediate Switches indicate support for LTR.
+ * PCIe r4.0, sec 6.18.
+ */
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
+ ((bridge = pci_upstream_bridge(dev)) &&
+ bridge->ltr_path)) {
pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_LTR_EN);
+ dev->ltr_path = 1;
+ }
#endif
}