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| author |   Thierry Reding <treding@nvidia.com> | 2020-03-19 13:27:33 +0100 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2020-03-27 11:41:38 +0100 |
| commit | 66539e6eac708d47b5db8909b08cf9fbeac8a1db (patch) | |
| tree | f0a144c963aa559cbfb69c209b7cf64541c2105a /drivers/pinctrl | |
| parent | pinctrl: tegra: Fix whitespace issues for improved readability (diff) | |
| download | wireguard-linux-66539e6eac708d47b5db8909b08cf9fbeac8a1db.tar.xz wireguard-linux-66539e6eac708d47b5db8909b08cf9fbeac8a1db.zip | |
pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
Properly spell "Schmitt" in the kerneldoc for pin group definitions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/tegra/pinctrl-tegra.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 0fc82eea9cf1..520865979d4a 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -107,7 +107,7 @@ struct tegra_function { * drvup, slwr, slwf, and drvtype parameters. * @drv_bank: Drive fields register bank. * @hsm_bit: High Speed Mode register bit. - * @schmitt_bit: Scmitt register bit. + * @schmitt_bit: Schmitt register bit. * @lpmd_bit: Low Power Mode register bit. * @drvdn_bit: Drive Down register bit. * @drvdn_width: Drive Down field width. |