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| author |   Grace Kao <grace.kao@intel.com> | 2020-04-17 12:11:54 +0800 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2020-04-17 14:37:40 +0300 |
| commit | 69388e15f5078c961b9e5319e22baea4c57deff1 (patch) | |
| tree | 5f73bc37cc42d5a6f80da8d071bc4f7355889d8b /drivers/pinctrl | |
| parent | pinctrl: baytrail: Enable pin configuration setting for GPIO chip (diff) | |
| download | wireguard-linux-69388e15f5078c961b9e5319e22baea4c57deff1.tar.xz wireguard-linux-69388e15f5078c961b9e5319e22baea4c57deff1.zip | |
pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler
According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")
Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers")
Signed-off-by: Grace Kao <grace.kao@intel.com>
Reported-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 4c74fdde576d..1093a6105d40 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) struct chv_pinctrl *pctrl = gpiochip_get_data(gc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; + unsigned long flags; u32 intr_line; chained_irq_enter(chip, desc); + raw_spin_lock_irqsave(&chv_lock, flags); pending = readl(pctrl->regs + CHV_INTSTAT); + raw_spin_unlock_irqrestore(&chv_lock, flags); + for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { unsigned int irq, offset; |