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| author |   Thinh Nguyen <Thinh.Nguyen@synopsys.com> | 2019-08-08 16:39:42 -0700 |
|---|---|---|
| committer |   Felipe Balbi <felipe.balbi@linux.intel.com> | 2019-08-09 08:31:38 +0300 |
| commit | 4749e0e61241cc121de572520a39dab365b9ea1d (patch) | |
| tree | 9bb5f9f08c454d35eed983c0e2bd2ef70e5f3612 /drivers/usb/dwc3/host.c | |
| parent | usb: dwc3: omap: squash include/linux/platform_data/dwc3-omap.h (diff) | |
| download | wireguard-linux-4749e0e61241cc121de572520a39dab365b9ea1d.tar.xz wireguard-linux-4749e0e61241cc121de572520a39dab365b9ea1d.zip | |
usb: dwc3: Update soft-reset wait polling rate
Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit
will not be cleared until after all the internal clocks are synchronized
during soft-reset. This may take a little more than 50ms. Set the
polling rate at 20ms instead.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc3/host.c')
0 files changed, 0 insertions, 0 deletions