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authorStephen Boyd <sboyd@kernel.org>2020-08-03 15:07:08 -0700
committerStephen Boyd <sboyd@kernel.org>2020-08-03 15:07:08 -0700
commit1a91e318c09777f4708c38d6fb98f4da47d9e067 (patch)
tree05836b24229bd9305d9901e5bd990615181a028d /include/dt-bindings
parentMerge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next (diff)
parentclk: davinci: Use fallthrough pseudo-keyword (diff)
parentclk: X1000: Add support for calculat REFCLK of USB PHY. (diff)
parentclk: tegra: pll: Improve PLLM enable-state detection (diff)
parentclk: clk-atlas6: fix return value check in atlas6_clk_init() (diff)
parentclk: qoriq: add LS1021A core pll mux options (diff)
downloadwireguard-linux-1a91e318c09777f4708c38d6fb98f4da47d9e067.tar.xz
wireguard-linux-1a91e318c09777f4708c38d6fb98f4da47d9e067.zip
Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and 'clk-qoriq' into clk-next
- Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs * clk-fallthru: clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword * clk-ingenic: clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. * clk-tegra: clk: tegra: pll: Improve PLLM enable-state detection * clk-sirf: clk: clk-atlas6: fix return value check in atlas6_clk_init() * clk-qoriq: clk: qoriq: add LS1021A core pll mux options