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| author |   Leo Yan <leo.yan@arm.com> | 2026-02-26 09:23:51 +0000 |
|---|---|---|
| committer |   Suzuki K Poulose <suzuki.poulose@arm.com> | 2026-03-03 10:23:45 +0000 |
| commit | b4d9ef475ec71e13e1ec395e9b9e6b165506a564 (patch) | |
| tree | 22860168458d5f1ad8590e4d567784575bc963a8 /include/linux/bcma/ssh:/git@git.zx2c4.com/git: | |
| parent | coresight: cti: Fix register reads (diff) | |
coresight: cti: Access ASICCTL only when implemented
According to the Arm ARM (DDI 0487 L.b), ASICCTL is implemented only
when CTIDEVID.EXTMUXNUM is non-zero.
Based on CTIDEVID.EXTMUXNUM, add a flag 'asicctl_impl' to indicate
whether the register is implemented, and access ASICCTL conditionally
based on the flag.
Allow the sysfs node to be visible only when the register is
implemented.
Reviewed-by: Mike Leach <mike.leach@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20260226-arm_coresight_cti_refactor_v1-v2-3-b30fada3cfec@arm.com
Diffstat (limited to 'include/linux/bcma/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions