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| author |   Robert Hancock <robert.hancock@calian.com> | 2021-02-16 16:54:52 -0600 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2021-02-16 15:23:23 -0800 |
| commit | 3afd0218992a8d1398e9791d6c2edd4c948ae7ee (patch) | |
| tree | 5583eee50cabe4500cab4c34ae5df6b0bc4271a5 /include/linux/brcmphy.h | |
| parent | lan743x: sync only the received area of an rx ring buffer (diff) | |
| download | wireguard-linux-3afd0218992a8d1398e9791d6c2edd4c948ae7ee.tar.xz wireguard-linux-3afd0218992a8d1398e9791d6c2edd4c948ae7ee.zip | |
net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for BCM54616S
The default configuration for the BCM54616S PHY may not match the desired
mode when using 1000BaseX or SGMII interface modes, such as when it is on
an SFP module. Add code to explicitly set the correct mode using
programming sequences provided by Bel-Fuse:
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-05-series.pdf
https://www.belfuse.com/resources/datasheets/powersolutions/ds-bps-sfp-1gbt-06-series.pdf
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
| -rw-r--r-- | include/linux/brcmphy.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 8fe1d55371ac..c2c2147dfeb8 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -129,6 +129,7 @@ #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 @@ -216,6 +217,9 @@ /* 11111: Mode Control Register */ #define BCM54XX_SHD_MODE 0x1f #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ +#define BCM54XX_SHD_INTF_SEL_RGMII 0x02 +#define BCM54XX_SHD_INTF_SEL_SGMII 0x04 +#define BCM54XX_SHD_INTF_SEL_GBIC 0x06 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ /* |