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| author |   Rex Zhu <rex.zhu@amd.com> | 2018-07-17 18:31:50 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-07-20 14:24:00 -0500 |
| commit | 97e8f102f5a9123d30258e196c6c1ea29cf52e83 (patch) | |
| tree | b7b8e70b9644d9061ccb01e959876ece07c7d356 /include/linux/compiler-gcc.h | |
| parent | drm/amd/pp: Update clk with od setting when set power state (diff) | |
| download | wireguard-linux-97e8f102f5a9123d30258e196c6c1ea29cf52e83.tar.xz wireguard-linux-97e8f102f5a9123d30258e196c6c1ea29cf52e83.zip | |
drm/amd/pp: Set Max clock level to display by default
avoid the error in dmesg:
[drm:dm_pp_get_static_clocks]
*ERROR* DM_PPLIB: invalid powerlevel state: 0!
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions