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| author |   Jon Hunter <jonathanh@nvidia.com> | 2015-05-05 15:17:53 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-05-10 19:12:18 +0200 |
| commit | 11e71007a5652dce2528a5d2451fe2697c6a370a (patch) | |
| tree | 523bc8985b6aeb782d6787c16c35db250be9a506 /include/linux/console_struct.h | |
| parent | serial: tegra: Correct delay after TX flush (diff) | |
| download | wireguard-linux-11e71007a5652dce2528a5d2451fe2697c6a370a.tar.xz wireguard-linux-11e71007a5652dce2528a5d2451fe2697c6a370a.zip | |
serial: tegra: Add delay after enabling FIFO mode
For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 3 UART clock periods after enabling
the TX fifo, otherwise data could be lost.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/console_struct.h')
0 files changed, 0 insertions, 0 deletions