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| author |   Jon Hunter <jonathanh@nvidia.com> | 2015-05-05 15:17:52 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-05-10 19:12:18 +0200 |
| commit | 245c0278ab2a2e3d0360296710b4c285291469b5 (patch) | |
| tree | 30fb45f2883375fc903d9f0500e5fff0c2c8d292 /include/linux/console_struct.h | |
| parent | serial: of_serial: do not set port.type twice (diff) | |
| download | wireguard-linux-245c0278ab2a2e3d0360296710b4c285291469b5.tar.xz wireguard-linux-245c0278ab2a2e3d0360296710b4c285291469b5.zip | |
serial: tegra: Correct delay after TX flush
For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 32 UART clock periods for the flush
to propagate otherwise TX data could be post. Add a helper function
to wait for N UART clock periods and update delay following FIFO
flush to be 32 UART clock cycles.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/console_struct.h')
0 files changed, 0 insertions, 0 deletions