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| author |   chenhui zhao <chenhui.zhao@freescale.com> | 2015-11-20 17:13:58 +0800 |
|---|---|---|
| committer |   Scott Wood <oss@buserror.net> | 2016-03-04 23:44:51 -0600 |
| commit | e7affb1dba0e9068aeb3978e858f39753e0dc20a (patch) | |
| tree | acc3b13685888fd5ad9ba6a67b0b6235447eba7f /include/linux/fsl | |
| parent | powerpc/mm: any thread in one core can be the first to setup TLB1 (diff) | |
| download | wireguard-linux-e7affb1dba0e9068aeb3978e858f39753e0dc20a.tar.xz wireguard-linux-e7affb1dba0e9068aeb3978e858f39753e0dc20a.zip | |
powerpc/cache: add cache flush operation for various e500
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches inside the current cpu.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@feescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'include/linux/fsl')
0 files changed, 0 insertions, 0 deletions