diff options
| author |   Nishanth Menon <nm@ti.com> | 2014-06-12 17:15:22 +0530 |
|---|---|---|
| committer |   Tony Lindgren <tony@atomide.com> | 2014-07-21 23:32:51 -0700 |
| commit | 76be4a54157ab0059fb29d8d516db46d239812e2 (patch) | |
| tree | 434db5329e5a6facbc1ca84bfac6c20daf9c7972 /include/linux/omap-dma.h | |
| parent | Merge tag 'for-v3.17/omap-clock-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.17/soc (diff) | |
| download | wireguard-linux-76be4a54157ab0059fb29d8d516db46d239812e2.tar.xz wireguard-linux-76be4a54157ab0059fb29d8d516db46d239812e2.zip | |
ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driver
we have currently 2 DMA drivers that try to co-exist.
drivers/dma/omap-dma.c which registers it's own IRQ and is device tree
aware and uses arch/arm/plat-omap/dma.c instance created by
arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma).
Currently both try to register interrupts and mach-omap2/plat-omap dma.c
attempts to use the IRQ number registered by hwmod to register it's own
interrupt handler.
Now, there is no reasonable way of static allocating DMA irq in GIC
SPI when we use crossbar. However, since the dma_chan structure is
freed as a result of IRQ not being present due to devm allocation,
maintaining information of channel by platform code fails at a later
point in time when that region of memory is reused.
So, if hwmod does not indicate an IRQ number, then, assume that
dma-engine will take care of the interrupt handling.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/linux/omap-dma.h')
| -rw-r--r-- | include/linux/omap-dma.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index 88e6ea4a5d36..6f06f8bc612c 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -130,6 +130,7 @@ #define IS_WORD_16 BIT(0xd) #define ENABLE_16XX_MODE BIT(0xe) #define HS_CHANNELS_RESERVED BIT(0xf) +#define DMA_ENGINE_HANDLE_IRQ BIT(0x10) /* Defines for DMA Capabilities */ #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) |