diff options
| author |   Lubomir Rintel <lkundrak@v3.sk> | 2019-08-08 15:47:24 +0200 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2019-10-17 16:36:12 +0200 |
| commit | 32adcaa010fa85e09296a6a606ad07348ef349ed (patch) | |
| tree | 98f30c6e716ba91e63ccfc0d01e2a64c1a854f20 /include/linux/soc | |
| parent | ARM: mmp: add SMP support (diff) | |
| download | wireguard-linux-32adcaa010fa85e09296a6a606ad07348ef349ed.tar.xz wireguard-linux-32adcaa010fa85e09296a6a606ad07348ef349ed.zip | |
ARM: mmp: move cputype.h to include/linux/soc/
Let's move cputype.h away from mach-mmp/ so that the drivers outside that
directory are able to tell the precise silicon revision. The MMP3 USB OTG
PHY driver needs this.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Diffstat (limited to 'include/linux/soc')
| -rw-r--r-- | include/linux/soc/mmp/cputype.h | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/include/linux/soc/mmp/cputype.h b/include/linux/soc/mmp/cputype.h new file mode 100644 index 000000000000..c3ec88983e94 --- /dev/null +++ b/include/linux/soc/mmp/cputype.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_CPUTYPE_H +#define __ASM_MACH_CPUTYPE_H + +#include <asm/cputype.h> + +/* + * CPU Stepping CPU_ID CHIP_ID + * + * PXA168 S0 0x56158400 0x0000C910 + * PXA168 A0 0x56158400 0x00A0A168 + * PXA910 Y1 0x56158400 0x00F2C920 + * PXA910 A0 0x56158400 0x00F2C910 + * PXA910 A1 0x56158400 0x00A0C910 + * PXA920 Y0 0x56158400 0x00F2C920 + * PXA920 A0 0x56158400 0x00A0C920 + * PXA920 A1 0x56158400 0x00A1C920 + * MMP2 Z0 0x560f5811 0x00F00410 + * MMP2 Z1 0x560f5811 0x00E00410 + * MMP2 A0 0x560f5811 0x00A0A610 + * MMP3 A0 0x562f5842 0x00A02128 + * MMP3 B0 0x562f5842 0x00B02128 + */ + +extern unsigned int mmp_chip_id; + +#ifdef CONFIG_CPU_PXA168 +static inline int cpu_is_pxa168(void) +{ + return (((read_cpuid_id() >> 8) & 0xff) == 0x84) && + ((mmp_chip_id & 0xfff) == 0x168); +} +#else +#define cpu_is_pxa168() (0) +#endif + +/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */ +#ifdef CONFIG_CPU_PXA910 +static inline int cpu_is_pxa910(void) +{ + return (((read_cpuid_id() >> 8) & 0xff) == 0x84) && + (((mmp_chip_id & 0xfff) == 0x910) || + ((mmp_chip_id & 0xfff) == 0x920)); +} +#else +#define cpu_is_pxa910() (0) +#endif + +#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT) +static inline int cpu_is_mmp2(void) +{ + return (((read_cpuid_id() >> 8) & 0xff) == 0x58) && + (((mmp_chip_id & 0xfff) == 0x410) || + ((mmp_chip_id & 0xfff) == 0x610)); +} +#else +#define cpu_is_mmp2() (0) +#endif + +#ifdef CONFIG_MACH_MMP3_DT +static inline int cpu_is_mmp3(void) +{ + return (((read_cpuid_id() >> 8) & 0xff) == 0x58) && + ((mmp_chip_id & 0xffff) == 0x2128); +} + +static inline int cpu_is_mmp3_a0(void) +{ + return (cpu_is_mmp3() && + ((mmp_chip_id & 0x00ff0000) == 0x00a00000)); +} + +static inline int cpu_is_mmp3_b0(void) +{ + return (cpu_is_mmp3() && + ((mmp_chip_id & 0x00ff0000) == 0x00b00000)); +} + +#else +#define cpu_is_mmp3() (0) +#define cpu_is_mmp3_a0() (0) +#define cpu_is_mmp3_b0() (0) +#endif + +#endif /* __ASM_MACH_CPUTYPE_H */ |