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authorVenkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>2018-09-12 11:06:33 -0700
committerAndy Gross <andy.gross@linaro.org>2018-09-13 15:53:58 -0500
commitc081f3060fab316fcf103967a24e502d58488849 (patch)
tree8e6e4f2dc4426a126ec08ed2880186a7883af7a1 /include/linux/soc
parentsoc: qcom: Add broadcast base for Last Level Cache Controller (LLCC) (diff)
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soc: qcom: Add support to register LLCC EDAC driver
Cache error reporting controller detects and reports single and double bit errors on Last Level Cache Controller (LLCC) cache. Add required support to register LLCC EDAC driver as platform driver, from LLCC driver. Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'include/linux/soc')
-rw-r--r--include/linux/soc/qcom/llcc-qcom.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index c681e795b587..2e4b34d2617e 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -78,6 +78,7 @@ struct llcc_slice_config {
* @num_banks: Number of llcc banks
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
+ * @ecc_irq: interrupt for llcc cache error detection and reporting
*/
struct llcc_drv_data {
struct regmap *regmap;
@@ -89,6 +90,7 @@ struct llcc_drv_data {
u32 num_banks;
unsigned long *bitmap;
u32 *offsets;
+ int ecc_irq;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)