|author||Ian Munsie <firstname.lastname@example.org>||2016-07-14 07:17:01 +1000|
|committer||Michael Ellerman <email@example.com>||2016-07-14 20:26:33 +1000|
|parent||powerpc/powernv: Split cxl code out into a separate file (diff)|
cxl: Add cxl_slot_is_supported API
This extends the check that the adapter is in a CAPI capable slot so that it may be called by external users in the kernel API. This will be used by the upcoming Mellanox CX4 support, which needs to know ahead of time if the card can be switched to cxl mode so that it can leave it in PCI mode if it is not. This API takes a parameter to check if CAPP DMA mode is supported, which it currently only allows on P8NVL systems, since that mode currently has issues accessing memory < 4GB on P8, and we cannot realistically avoid that. This API does not currently check if a CAPP unit is available (i.e. not already assigned to another PHB) on P8. Doing so would be racy since it is assigned on a first come first serve basis, and so long as CAPP DMA mode is not supported on P8 we don't need this, since the only anticipated user of this API requires CAPP DMA mode. Cc: Philippe Bergheaud <firstname.lastname@example.org> Signed-off-by: Ian Munsie <email@example.com> Reviewed-by: Andrew Donnellan <firstname.lastname@example.org> Reviewed-by: Frederic Barrat <email@example.com> Signed-off-by: Michael Ellerman <firstname.lastname@example.org>
Diffstat (limited to 'include/misc')
1 files changed, 15 insertions, 0 deletions
diff --git a/include/misc/cxl.h b/include/misc/cxl.h
index b6d040f31f76..dd9eebba3bb6 100644
@@ -24,6 +24,21 @@
* generic PCI API. This API is agnostic to the actual AFU.
+#define CXL_SLOT_FLAG_DMA 0x1
+ * Checks if the given card is in a cxl capable slot. Pass CXL_SLOT_FLAG_DMA if
+ * the card requires CAPP DMA mode to also check if the system supports it.
+ * This is intended to be used by bi-modal devices to determine if they can use
+ * cxl mode or if they should continue running in PCI mode.
+ * Note that this only checks if the slot is cxl capable - it does not
+ * currently check if the CAPP is currently available for chips where it can be
+ * assigned to different PHBs on a first come first serve basis (i.e. P8)
+bool cxl_slot_is_supported(struct pci_dev *dev, int flags);
/* Get the AFU associated with a pci_dev */
struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev);