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| author |   Zhiwu Song <zhiwu.song@csr.com> | 2011-08-30 19:20:34 -0700 |
|---|---|---|
| committer |   Barry Song <21cnbao@gmail.com> | 2011-09-11 09:17:53 +0800 |
| commit | 684f741446f7a3108b4c167faf20214c42b7eeac (patch) | |
| tree | 7d6b2d4919640170f61aaaf5460e9b2a6dbb24cd /ipc/msgutil.c | |
| parent | ARM: CSR: IRQ: add simple irq_domain so that hw irq can map to Linux (diff) | |
| download | wireguard-linux-684f741446f7a3108b4c167faf20214c42b7eeac.tar.xz wireguard-linux-684f741446f7a3108b4c167faf20214c42b7eeac.zip | |
ARM: CSR: add rtc i/o bridge interface for SiRFprimaII
The module is a bridge between the RTC clock domain and the CPU interface
clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through
this module.
Signed-off-by: Zhiwu Song <zhiwu.song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'ipc/msgutil.c')
0 files changed, 0 insertions, 0 deletions