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| author |   Ravi Bangoria <ravi.bangoria@amd.com> | 2025-02-05 06:05:42 +0000 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2025-02-17 15:20:05 +0100 |
| commit | 0b347a4218da08b1eb400c259d193bff463dae87 (patch) | |
| tree | 21d738fcb2e8da0bc0379fe9c7bf9acf7c01e816 /kernel/sysctl.c | |
| parent | perf/amd/ibs: Add support for OP Load Latency Filtering (diff) | |
| download | wireguard-linux-0b347a4218da08b1eb400c259d193bff463dae87.tar.xz wireguard-linux-0b347a4218da08b1eb400c259d193bff463dae87.zip | |
perf/amd/ibs: Update DTLB/PageSize decode logic
IBS Op PMU on Zen5 reports DTLB and page size information differently
compared to prior generation. The change is enumerated by
CPUID_Fn8000001B_EAX[19].
IBS_OP_DATA3 Zen3/4 Zen5
----------------------------------------------------------------
19 IbsDcL2TlbHit1G Reserved
----------------------------------------------------------------
6 IbsDcL2tlbHit2M Reserved
----------------------------------------------------------------
5 IbsDcL1TlbHit1G PageSize:
4 IbsDcL1TlbHit2M 0 - 4K
1 - 2M
2 - 1G
3 - Reserved
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
3 IbsDcL2TlbMiss IbsDcL2TlbMiss
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
2 IbsDcL1tlbMiss IbsDcL1tlbMiss
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
o Currently, only bit 2 and 3 are interpreted by IBS NMI handler for
PERF_SAMPLE_DATA_SRC. Add dependency on IbsDcPhyAddrValid for those
bits.
o Introduce new IBS Op PMU capability and expose it to userspace via
PMU's sysfs directory.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250205060547.1337-3-ravi.bangoria@amd.com
Diffstat (limited to 'kernel/sysctl.c')
0 files changed, 0 insertions, 0 deletions