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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-06-01 12:49:32 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-10 12:10:07 -0700 |
| commit | ee800010835db23c70acc01000f182955cab27a5 (patch) | |
| tree | bb7678bc2cd22ea26b50b23f772d1124de3e61d9 /kernel | |
| parent | tools/testing/cxl: Fix decoder default state (diff) | |
| download | wireguard-linux-ee800010835db23c70acc01000f182955cab27a5.tar.xz wireguard-linux-ee800010835db23c70acc01000f182955cab27a5.zip | |
cxl/port: Cache CXL host bridge data
Region creation has need for checking host-bridge connectivity when
adding endpoints to regions. Record, at port creation time, the
host-bridge to provide a useful shortcut from any location in the
topology to the most-significant ancestor.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-4-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions