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| author |   Jan Beulich <JBeulich@novell.com> | 2011-02-09 08:26:53 +0000 |
|---|---|---|
| committer |   Ingo Molnar <mingo@elte.hu> | 2011-02-10 13:32:52 +0100 |
| commit | 691269f0d918cd72454c254f97722f194c07b9a8 (patch) | |
| tree | bff65907c36cb8f8a3dc60796baf5964a547ba0e /lib/debugobjects.c | |
| parent | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs (diff) | |
| download | wireguard-linux-691269f0d918cd72454c254f97722f194c07b9a8.tar.xz wireguard-linux-691269f0d918cd72454c254f97722f194c07b9a8.zip | |
x86: Adjust section placement in AMD northbridge related code
amd_nb_misc_ids[] can live in .rodata, and enable_pci_io_ecs()
can be moved into .cpuinit.text.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: Andreas Herrmann <Andreas.Herrmann3@amd.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <4D525DDD0200007800030F07@vpn.id2.novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions