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| author | 2018-08-06 12:45:42 +0200 | |
|---|---|---|
| committer | 2018-08-06 12:45:42 +0200 | |
| commit | 9e90c7985229430428dc9ba0ec7fe422901b456d (patch) | |
| tree | cae2072feba8cc433a32d96568bbcf36070bd6e5 /lib/dec_and_lock.c | |
| parent | genirq/irqchip: Remove MULTI_IRQ_HANDLER as it's now obselete (diff) | |
| parent | irqchip/gic-v3-its: Make its_lock a raw_spin_lock_t (diff) | |
| download | wireguard-linux-9e90c7985229430428dc9ba0ec7fe422901b456d.tar.xz wireguard-linux-9e90c7985229430428dc9ba0ec7fe422901b456d.zip | |
Merge tag 'irqchip-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- GICv3 ITS LPI allocation revamp
- GICv3 support for hypervisor-enforced LPI range
- GICv3 ITS conversion to raw spinlock
Diffstat (limited to 'lib/dec_and_lock.c')
| -rw-r--r-- | lib/dec_and_lock.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/dec_and_lock.c b/lib/dec_and_lock.c index 347fa7ac2e8a..9555b68bb774 100644 --- a/lib/dec_and_lock.c +++ b/lib/dec_and_lock.c @@ -33,3 +33,19 @@ int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock) } EXPORT_SYMBOL(_atomic_dec_and_lock); + +int _atomic_dec_and_lock_irqsave(atomic_t *atomic, spinlock_t *lock, + unsigned long *flags) +{ + /* Subtract 1 from counter unless that drops it to 0 (ie. it was 1) */ + if (atomic_add_unless(atomic, -1, 1)) + return 0; + + /* Otherwise do it the slow way */ + spin_lock_irqsave(lock, *flags); + if (atomic_dec_and_test(atomic)) + return 1; + spin_unlock_irqrestore(lock, *flags); + return 0; +} +EXPORT_SYMBOL(_atomic_dec_and_lock_irqsave); |
