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author | 2019-07-24 17:00:06 +0100 | |
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committer | 2019-07-24 17:00:06 +0100 | |
commit | 27988c96687667e74df1a9a3b8662519bc1c29c9 (patch) | |
tree | 0aa67d365e8d544bf48a4de9ae94d7f8536de073 /lib/mpi/longlong.h | |
parent | regulator: axp20x: fix DCDC5 and DCDC6 for AXP803 (diff) | |
parent | Linus 5.3-rc1 (diff) | |
download | wireguard-linux-27988c96687667e74df1a9a3b8662519bc1c29c9.tar.xz wireguard-linux-27988c96687667e74df1a9a3b8662519bc1c29c9.zip |
Merge tag 'v5.3-rc1' into regulator-5.3
Linus 5.3-rc1
Diffstat (limited to '')
-rw-r--r-- | lib/mpi/longlong.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/mpi/longlong.h b/lib/mpi/longlong.h index 08c60d10747f..3bb6260d8f42 100644 --- a/lib/mpi/longlong.h +++ b/lib/mpi/longlong.h @@ -397,8 +397,8 @@ do { \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("addl %5,%1\n" \ "adcl %3,%0" \ - : "=r" ((USItype)(sh)), \ - "=&r" ((USItype)(sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "%0" ((USItype)(ah)), \ "g" ((USItype)(bh)), \ "%1" ((USItype)(al)), \ @@ -406,22 +406,22 @@ do { \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ __asm__ ("subl %5,%1\n" \ "sbbl %3,%0" \ - : "=r" ((USItype)(sh)), \ - "=&r" ((USItype)(sl)) \ + : "=r" (sh), \ + "=&r" (sl) \ : "0" ((USItype)(ah)), \ "g" ((USItype)(bh)), \ "1" ((USItype)(al)), \ "g" ((USItype)(bl))) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("mull %3" \ - : "=a" ((USItype)(w0)), \ - "=d" ((USItype)(w1)) \ + : "=a" (w0), \ + "=d" (w1) \ : "%0" ((USItype)(u)), \ "rm" ((USItype)(v))) #define udiv_qrnnd(q, r, n1, n0, d) \ __asm__ ("divl %4" \ - : "=a" ((USItype)(q)), \ - "=d" ((USItype)(r)) \ + : "=a" (q), \ + "=d" (r) \ : "0" ((USItype)(n0)), \ "1" ((USItype)(n1)), \ "rm" ((USItype)(d))) |